View PE42851MLBA-X_9057458.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

page 1 of 12 ?2012-2015 peregrine semiconductor corp. all rights reserved. document no. doc-13014-4 www.psemi.com figure 1. package type 32-lead 5 5 mm qfn product description the pe42851 is a harp? technology-enhanced sp5t high power rf switch supporting wireless applications up to 1 ghz. it offers maximum power handling of 42.5 dbm continuous wave (cw). it delivers high linearity and excellent harmonics performance. it has both a standard and attenuated rx mode. no blocking capacitors are required if dc voltage is not present on the rf ports. the pe42851 is manufactured on peregrine?s ultracmos ? process, a patented variation of silicon-on- insulator (soi) technology on a sapphire substrate, offering the performance of gaas with the economy and integration of conventional cmos. product specification ultracmos ? sp5t rf switch 100?1000 mhz pe42851 features ?? dual mode operation: sp5t or sp3t ?? harp? technology enhanced ?? fast settling time ?? no gate and phase lag ?? no drift in insertion loss and phase ?? up to 45 dbm instantaneous power in 50 ? ?? up to 40 dbm instantaneous power < 8:1 vswr ?? 36 db tx to rx isolation ?? low harmonics of 2f o and 3f o = ?80 dbc (1.15:1 vswr) ?? esd performance ?? 1.5 kv hbm on all pins ?? 1 kv cdm on all pins figure 2. functional diagram of sp3t configuration ant can be tied to tx1 and tx2 or tx3 and tx4 figure 3. functional diagram of sp5t configuration sp5t, standard configuration doc-02178
product specification pe42851 page 2 of 12 ?2012-2015 peregrine semiconductor corp. all rights reserved. document no. doc-13014-4 ultracmos ? rfic solutions table 1. electrical specifications @ ?40 to +85 c, v dd = 2.3?5.5v, v ss_ext = 0v or v dd = 3.4?5.5v, v ss_ext = ?3.4v (z s = z l = 50? ), unless otherwise noted 1 parameter path condition min typ max unit operating frequency 100 1000 mhz insertion loss 2 ant?tx active tx port 1, 2, 3 or 4 @ rated power (?40 c, +25 c) 100?520 mhz 520?1000 mhz 0.25 0.40 0.35 0.55 db db active tx port 1, 2, 3 or 4 @ rated power (+85 c) 100?520 mhz 520?1000 mhz 0.30 0.50 0.40 0.60 db db insertion loss 2 (un-attenuated state) ant?rx active rx port (?40 c, +25 c) 100?520 mhz 520?1000 mhz 0.60 0.70 0.70 0.90 db db active rx port (+85 c) 100?520 mhz 520?1000 mhz 0.70 0.80 0.80 1.00 db db 1575 mhz for gps rx, < ?10 dbm, +25 c 1.2 1.3 db insertion loss 2 (attenuated state) ant?rx active rx port 100?1000 mhz 15.2 16 16.8 db isolation (supply biased) tx?tx 100?520 mhz 520?1000 mhz 33 29 36 30 db db isolation (supply biased) tx?rx 100?520 mhz 520?1000 mhz 34 29 36 30 db db unbiased isolation v dd , v1, v2, v3 = 0v ant?tx +27 dbm 6 db unbiased isolation v dd , v1, v2, v3 = 0v ant?rx +27 dbm 14 db return loss 2 ant?rx un-attenuated state 100?520 mhz 520?1000 mhz 22 18 27 22 db db un-attenuated state, 1575 mhz for gps rx, < ?10 dbm, +25 c 10 14 db attenuated state, optimized without attenuator engaged 100?520 mhz 520?1000 mhz 16 13 21 18 db db return loss 2 ant?tx 100?520 mhz 520?1000 mhz 21 15 28 17 db db 2nd and 3rd harmonic (< 1.15:1 vswr) tx 100?520 mhz @ +40.0 dbm 521?870 mhz @ +38.5 dbm 871?1000 mhz @ +37.5 dbm ?80 ?78 dbc 2nd and 3rd harmonic (< 8:1 vswr) tx 100?520 mhz @ +40.0 dbm (pulsed signal, at 10% duty cycle 3 ) 521?870 mhz @ +38.5 dbm (pulsed signal, at 10% duty cycle 3 ) 871?1000 mhz @ +37.5 dbm (pulsed signal, at 10% duty cycle 3 ) ?76 ?70 dbc iip3 rx un-attenuated state attenuated state 42 38 dbm dbm settling time from 50% control until har monics within specifications 15 s 2nd and 3rd harmonic (50 ? source/load impedance) tx 100?1000 mhz @ +42.5 dbm (cw) ?78 ?74 dbc 2nd and 3rd harmonic (50 ? source/load impedance) tx 100?1000 mhz @ +45.0 dbm (pulsed signal, at 10% duty cycle 3 ) ?76 ?70 dbc switching time in bypass mode 4 (v ss_ext = ?3.4v) 50% ctrl to 90% or 10% of rf 4 s input 0.1db compression point 5 ant?tx 1000 mhz 45.5 dbm switching time in normal mode 4 (v ss_ext = 0v) 50% ctrl to 90% or 10% of rf 6 s notes: 1. in a 2tx?1rx sp3t configuration, tx1 and tx2 are tied and tx3 and tx4 are tied respectively. refer to application no te an35 for sp3t performance data. 2. narrow trace widths are used near each port to im prove impedance matching. refer to evaluation board layouts ( figure 23 ) and schematic ( figure 24 ) for details. 3. 10% of 4620 s period. 4. normal mode: connect v ss_ext (pin 16) to gnd (v ss_ext = 0v) to enable internal negative voltage generator. bypass mode: use v ss_ext (pin 16) to bypass and disable internal negative voltage generator. 5. the input 0.1db compression point is a linearity figure of merit. refer to table 3 for the rf input power p in.
product specification pe42851 page 3 of 12 ?2012-2015 peregrine semiconductor corp. all rights reserved. document no. doc-13014-4 www.psemi.com table 2. pin descriptions figure 4. pin configuration (top view)* pin # pin name description 1, 3, 5?7, 9? 11, 17?20, 22, 24?27, 29?32 gnd ground 2 tx1 2 transmit pin 1 4 tx2 1,2 transmit pin 2 8 rx 2 receive pin 12 v dd supply voltage (nominal 3.3v) 13 v3 digital control logic input 3 14 v2 digital control logic input 2 15 v1 digital control logic input 1 16 v ss_ext 3 external v ss negative voltage control 21 tx3 2 transmit pin 3 23 tx4 1,2 transmit pin 4 28 ant 2 antenna pin pad gnd exposed pad: ground for proper operation notes: 1. to operate the part as a 2tx?1rx sp3t, tie tx1 to tx2 and tx3 to tx4 respectively. refer to application note an35 for sp3t performance data. 2. rf pins 2, 4, 8, 21, 23 and 28 must be at 0 vdc. the rf pins do not require dc blocking capacitors for proper operation if the 0 vdc requirement is met. 3. use v ss_ext (pin 16) to bypass and disable internal negative voltage generator. connect v ss_ext (pin 16) to gnd (v ss_ext = 0v) to enable internal negative voltage generator. table 3. operating ranges 1 parameter symbol min typ max unit supply voltage (normal mode, v ss_ext = 0v) v dd 2.3 5.5 v supply voltage (bypass mode, v ss_ext = ?3.4v, v dd 3.4v for full spec. compliance) v dd 2.7 3.4 5.5 v negative supply voltage (bypass mode) v ss_ext ?3.6 ?3.2 v supply current (normal mode, v ss_ext = 0v) i dd 130 200 a supply current (bypass mode, v ss_ext = ?3.4v) i dd 50 80 a negative supply current (bypass mode, v ss_ext = ?3.4v) i ss ?40 ?16 a digital input high (v1, v2, v3) v ih 1.17 3.6 v digital input low (v1, v2, v3) v il ?0.3 0.6 v tx rf input power 2,3 (vswr 8:1) p in?tx 40 dbm tx rf input power 2,3 (50 ? source/load impedance) p in?tx 45 dbm tx rf input power 2 (50 ? source/load impedance, cw) p in?tx 42.5 dbm ant rf input power, unbiased (vswr 8:1) p in?ant 27 dbm rx rf input power 2 (vswr 8:1) p in?rx 27 dbm operating temperature range (case) t op ?40 85 c operating junction temperature t j 135 c notes: 1. in a 2tx?1rx sp3t configuration, tx1 and tx2 are tied and tx3 and tx4 are tied respectively. refer to application note an35 for sp3t performance data. 2. supply biased. 3. pulsed, 10% duty cycle of 4620 s period. 16 15 14 13 12 11 10 9 25 26 27 28 29 30 31 32 gnd gnd gnd v dd v3 v2 v1 v ss_ext gnd gnd gnd gnd ant gnd gnd gnd note: * pins 1, 3, 5, 7, 9, 10, 17, 19, 20, 22, 24, 26, 27, 29, 30 and 31 can be n/c if deemed necessary by the customer
product specification pe42851 page 4 of 12 ?2012-2015 peregrine semiconductor corp. all rights reserved. document no. doc-13014-4 ultracmos ? rfic solutions electrostatic discharge (esd) precautions when handling this ultracmos device, observe the same precautions that you would use with other esd-sensitive devices. although this device contains circuitry to protect it from damage due to esd, precautions should be taken to avoid exceeding the rating specified. latch-up avoidance unlike conventional cmos devices, ultracmos devices are immune to latch-up. moisture sensitivity level the moisture sensitivity level rating for the 5x5 mm qfn package is msl3. table 5. truth table path v3 v2 v1 ant ? rx attenuated l l l ant ? tx1 l l h ant ? tx2 l h l ant ? tx1 and tx2* l h h ant ? rx h l l ant ? tx3 h l h ant ? tx4 h h l ant ? tx3 and tx4* h h h exceeding absolute maximum ratings may cause permanent damage. operation should be restricted to the limits in the operating ranges table. operation between operating range maximum and absolute maximum for extended periods may reduce reliability. table 4. absolute maximum ratings parameter/condition symbol min max unit supply voltage v dd ?0.3 5.5 v digital input voltage (v1, v2, v3) v ctrl ?0.3 3.6 v tx rf input power 1 (50 ? source/load impedance) p in?tx 45 dbm tx rf input power 1 (vswr 8:1) p in?tx 40 dbm ant rf input power, unbiased (vswr 8:1) p in?ant 27 dbm rx rf input power 1 (vswr 8:1) p in?rx 27 dbm storage temperature range t st ?65 150 c maximum case temperature t case 85 c peak maximum junction temperature (10 seconds max) t j 200 c esd voltage hbm 2 , all pins v esd,hbm 1500 v esd voltage mm 3 , all pins v esd,mm 200 v esd voltage cdm 4 , all pins v esd,cdm 1000 v notes: 1. supply biased 2. human body model (mil-std 883 method 3015) 3. machine model (jedec jesd22-a115) 4. charged device model (jedec jesd22-c101) switching frequency the pe42851 has a maximum 10 khz switching rate when the internal negative voltage generator is used (pin 16 = gnd). the rate at which the pe42851 can be switched is only limited to the switching time ( table 1 ) if an external negative supply is provided (pin 16 = v ss_ext ). switching frequency describes the time duration between switching events. switching time is the time duration between the point the control signal reaches 50% of the final value and the point the output signal reaches within 10% or 90% of its target value. spurious performance the typical spurious performance of the pe42851 is ?130 dbm when v ss_ext = 0v (pin 16 = gnd). if further improvement is desired, the internal negative voltage generator can be disabled by setting v ss_ext = ?3.4v. optional external v ss control (v ss_ext ) for proper operation, the v ss_ext control pin must be grounded or tied to the vss voltage specified in table 3 . when the v ss_ext control pin is grounded, fets in the switch are biased with an internal voltage generator. for applications that require the lowest possible spur performance, v ss_ext can be applied externally to bypass the internal negative voltage generator. note: * in a 2tx?1rx sp3t configuration, tx1 and tx2 are tied and tx3 and tx4 are tied respectively. refer to application note an35 for sp3t performance data.
product specification pe42851 page 5 of 12 ?2012-2015 peregrine semiconductor corp. all rights reserved. document no. doc-13014-4 www.psemi.com typical performance data @ +25 c and v dd = 3.4v, unless otherwise specified figure 5. insertion loss vs. temp (tx) figure 6. insertion loss vs. v dd (tx) figure 8. insertion loss vs. v dd (rx, un-attenuated) figure 7. insertion loss vs. temp (rx, un-attenuated) figure 9. insertion loss vs. temp (rx, attenuated) figure 10. insertion loss vs. v dd (rx, attenuated)
product specification pe42851 page 6 of 12 ?2012-2015 peregrine semiconductor corp. all rights reserved. document no. doc-13014-4 ultracmos ? rfic solutions typical performance data @ +25 c and v dd = 3.4v, unless otherwise specified figure 11. return loss vs. temp (ant) figure 12. return loss vs. v dd (ant) figure 13. return loss vs. temp (tx) figure 14. return loss vs. v dd (tx) figure 15. return loss vs. temp (rx, attenuated) figure 16. return loss vs. v dd (rx, attenuated)
product specification pe42851 page 7 of 12 ?2012-2015 peregrine semiconductor corp. all rights reserved. document no. doc-13014-4 www.psemi.com typical performance data @ +25 c and v dd = 3.4v, unless otherwise specified figure 19. isolation vs. temp (tx?tx) figure 20. isolation vs. v dd (tx?tx) figure 21. isolation vs. temp (tx?rx) figure 22. isolation vs. v dd (tx?rx) figure 17. return loss vs. temp (rx, un-attenuated) figure 18. return loss vs. v dd (rx, un-attenuated)
product specification pe42851 page 8 of 12 ?2012-2015 peregrine semiconductor corp. all rights reserved. document no. doc-13014-4 ultracmos ? rfic solutions thermal data though the insertion loss for this part is very low, when handling high power rf signals, the junction temperature rises significantly. vswr conditions that present short circuit loads to the part can cause significantly more power dissipation than with proper matching. special consideration needs to be made in the design of the pcb to properly dissipate the heat away from the part and maintain the +85 c maximum case temperature. it is recommended to use best design practices for high power qfn packages: multi-layer pcbs with thermal vias in a thermal pad soldered to the slug of the package. special care also needs to be made to alleviate solder voiding under the part. table 6. theta jc parameter min typ max unit theta jc (+85 c) 20 ? c/w
product specification pe42851 page 9 of 12 ?2012-2015 peregrine semiconductor corp. all rights reserved. document no. doc-13014-4 www.psemi.com evaluation kit the pe42851 evaluation kit board was designed to ease customer evaluation of the pe42851 rf switch. the evaluation board in figure 23 was designed to test the part in the 5t configuration. dc power is supplied through j10, with v dd on pin 9, and gnd on the entire lower row of even numbered pins. to evaluate a switch path, add or remove jumpers on v1 (pin 3), v2 (pin 5), and v3 (pin 7) using table 5 (adding a jumper pulls the cmos control pin low and removing it allows the on-board pull-up resistor to set the cmos control pin high). pins 11 and 13 of j10 are n/c. the ant port is connected through a 50 ? transmission line via the top sma connector, j1. rx and tx paths are also connected through 50 ? transmission lines via sma connectors. a 50? through transmission line is available via sma connectors j8 and j9. this transmission line can be used to estimate the loss of the pcb over the environmental conditions being evaluated. an open-ended 50 ? transmission line is also provided at j7 for calibration if needed. narrow trace widths are used near each part to improve impedance matching. figure 23. evaluation board layouts prt-50283
product specification pe42851 page 10 of 12 ?2012-2015 peregrine semiconductor corp. all rights reserved. document no. doc-13014-4 ultracmos ? rfic solutions figure 24. evaluation board schematic doc-13027 notes: 1. use 101-0316-02 pcb 2. 32 mil width, 10 mil gaps, 28 mil core, 4.3 er, and 2.1 mil cu
product specification pe42851 page 11 of 12 ?2012-2015 peregrine semiconductor corp. all rights reserved. document no. doc-13014-4 www.psemi.com top view bottom view side view recommended land pattern a 0.10 c (2x) c 0.10 c 0.05 c seating plane b 0.10 c (2x) 0.10 c a b 0.05 c all features pin #1 corner 5.00 5.00 3.300.05 3.300.05 3.50 3.50 0.50 0.240.05 (x32) 0.3750.05 (x32) 0.203 ref. 0.05 0.850.05 0.575 (x32) 0.290 (x32) 3.35 5.20 3.35 5.20 0.50 (x28) detail a 1 8 9 16 17 24 25 32 0.18 0.15 0.10 detail a doc-01872 figure 25. package drawing 32-lead 5x5 mm qfn figure 26. top marking specification 42851 yyww zzzzzz 17-0085 = pin 1 designator yyww = date code, last two digits of the year and work week zzzzzz = six digits of the lot number
product specification pe42851 page 12 of 12 ?2012-2015 peregrine semiconductor corp. all rights reserved. document no. doc-13014-4 ultracmos ? rfic solutions table 7. ordering information figure 27. tape and reel drawing order code description package shipping method PE42851MLBA-X pe42851 sp5t rf switch green 32-lead 5 5 mm qfn 500 units / t&r ek42851-03 pe42851 evaluation ki t evaluation kit 1 / box notes: 1. 10 sprocket hole pitch cumulative tolerance 0.02. 2. camber not to exceed 1 mm in 100 mm. 3. material: ps + c. 4. ao and bo measured as indicated. 5. ko measured from a plane on the inside bottom of the pocket to the top surface of the carrier. 6. pocket position relative to sprocket hole measured as true position of pocket, not pocket hole. ao = 5.25 mm bo = 5.25 mm ko = 1.1 mm device orientation in tape top of device pin 1 tape feed direction advance information: the product is in a formative or design stage. the datasheet contains design target specifications for product development. specifications and features may change in any manner without notice. preliminary specification: the datasheet contains preliminary data. additional data may be added at a later date. peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. product specification: the datasheet contains final data. in the event peregrine decides to change the specifications, peregrine will notify custom ers of the intended changes by issuing a cnf (customer notification form). the information in this datasheet is believed to be reliable. however, peregrine assumes no liability for the use of this information. use shall be entirely at the user?s own risk. no patent rights or licenses to any circuits described in this datasheet are implied or granted to any third party. peregrine?s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the peregrine product could create a situation in which personal injury or death might occur. peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. the peregrine name, logo, ultracmos and utsi are registered trademarks and harp, multiswitch and dune are trademarks of peregrine semiconductor corp. peregrine products are protected under one or more of the following u.s. patents: http://patents.psemi.com . sales contact and information for sales and contact information please visit www.psemi.com .

▲Up To Search▲

Price & Availability of PE42851MLBA-X

	To Download PE42851MLBA-X Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .